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Chang Eun (Paul) Song
Contact: [email protected] | Personal Website: www.changeunsong.com
EDUCATION
University of California, San Diego La Jolla, CA
Ph.D. Candidate, Computer Science, GPA of 3.93/4.0 Sep. 2022 – Dec.2026 (expect)
M.S, Computer Science Sep. 2022 - Dec. 2024
Korea University Seoul, Korea
B.E, Electrical Engineering, GPA of 4.17/4.5 (Major GPA of 4.43/4.5) Mar. 2016 – Feb. 2022
RESEARCH INTERESTS
Hardware/Software Co-Design for AI Accelerator & Architecture
Digital & Mixed-Signal Chip Design and Processing-in-Memory (PIM)
Optimizations for Large Language Models (LLMs), Retrieval-Augmented Generation (RAG), Neuromorphic Computing
SELECTED PUBLICATIONS (*co-first author) [P]
[10] (Preprint) W. Xu*, C. E. Song*, et al., T. Rosing, and M. Kang
“FSL-HDnn: A 40nm Multi-purpose On-Device Learning Accelerator with Integrated Feature Extraction and Hyperdimensional
Computing Enabling Fast Edge AI Applications”, IEEE Journal of Solid-State Circuits. (under review)
[9] (CICC’26) S. E. Kim, C. E. Song, et al., T. Rosing, and M. Kang
“A 4D Radar Accelerator with Adaptive Sparse Processing for Real-Time Object Detection”, IEEE Custom Integrated Circuits
Conference, 2026.
[8] (IEDM’25) Y. Zhou, Y. Zhou, A. Kumar, W. Xu, C. E. Song, et al., T. Rosing, and D. Kuzum
“8-Layer Vertical Filament-Free Bulk RRAM with High Dynamic Range and Energy Efficiency for 3D Multilevel Compute-in- Memory”, IEEE International Electron Devices Meeting, 2025.
[7] (JSSC’25) C. E. Song, et al., T. Rosing, and M. Kang
“Energy-efficient Reconfigurable XGBoost Inference Accelerator with Modular Unit Trees via Selective Node Execution and
Data Movement”, IEEE Journal of Solid-State Circuits, 2025. [Link]
[6] (HOTCHIPS’25) C. E. Song, et al., T. Rosing, and M. Kang
“Clo-HDnn: Continual On-Device Learning Accelerator with Hyperdimensional Computing via Progressive Search”, IEEE Hot
Chips Symposium, 2025. [Link]
[5] (ISCA’25) C. E. Song, et al., T. Rosing, and M. Kang
“Hybrid SLC-MLC RRAM Mixed-Signal Processing-in-Memory Architecture for Transformer Acceleration via Gradient
Redistribution”, ACM/IEEE International Symposium on Computer Architecture, 2025. [Link]
(Invited at Mondays in Memory (MiM) Webinar)
- ACM Artifact Review Badges: Artifact Available, Artifact Evaluated
[4] (VLSI’25) C. E. Song, et al., T. Rosing, and M. Kang
“Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-efficient
Hyperdimensional Computing via Progressive Search”, IEEE Symposium on VLSI Technology and Circuits, 2025. [Link]
(Invited at CogSense @MICRO25 Workshop)
[3] (ESSERC’24) H. Yang*, C. E. Song*, et al., M. Kang, and T. Rosing
“FSL-HDnn: A 5.7 TOPS/W End-to-end Few-shot Learning Classifier Accelerator with Feature Extraction and
Hyperdimensional Computing”, IEEE European Solid-State Electronics Research Conference, 2024. [Link]
[2] (ISLPED’24) C. E. Song, et al., T. Rosing, and M. Kang
“Efficient Transformer Acceleration via Reconfiguration for Encoder and Decoder Models and Sparsity-Aware Algorithm
Mapping”, ACM/IEEE International Symposium on Low Power Electronics and Design, 2024. [Link]
[1] (CICC’24) C. E. Song, et al., T. Rosing, and M. Kang
“52.5 TOPS/W 1.7GHz Reconfigurable XGBoost Inference Accelerator based on Modular-Unit-Tree with Dynamic Data and
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Compute Gating”, IEEE Custom Integrated Circuits Conference, 2024. [Link]
WORK EXPERIENCE
AI Hardware Research Intern, TSMC Technology, Inc San Jose, CA
(Manager: Kerem Akarvardar) Jun. 2024 –Sep. 2024
• Performed research and developed circuit–architecture co-optimization for LLM softmax using MX data type.
RESEARCH EXPERIENCE
Graduate Student Researcher, UC San Diego La Jolla, CA
- Vertically-integrated VLSI Information Processing LAB (Co-advisor: Prof. Mingu Kang) Sep. 2022 – Present
- System Energy Efficiency LAB (Co-advisor: Prof. Tajana Šimunić Rosing) Jan. 2023 – Present
• In-storage searching in 3D NAND for efficient RAG system for LLM accelerator. (Under Review)
• Clo-HDnn; Led the physical design flow for a mixed-signal chip fabricated in TSMC 40nm CMOS, including front-end
(RTL design) and back-end (syn & pnr). Implementing continual on-device learning using hyperdimensional (HD)
computing via efficient HD encoder and progressive search, ensuring energy-efficient operation in a reconfigurable
environment. [P.4] [P.6]
• Significance-Driven MLC-SLC Hybrid Mixed PIM Transformer Accelerator; Built an open source PIM simulator; LLM
optimization & RTL design in TSMC 65nm CMOS; Achieving 1.86× throughput & 1.49× energy efficiency vs. SoTA.
[P.5]
• FSL-HDnn: Few shot learning with efficient feature extractor and hyperdimensional computing classifier; Led the front- end (RTL design) and back-end physical design flow (syn & pnr) for a digital chip fabricated in TSMC 40nm CMOS;
2.6× for feature extraction, and 6.6× for classification energy efficient than SoTA. [P.3]
• Transformer Acceleration via Reconfiguration for Encoder and Decoder Models; LLM optimization & RTL design in
TSMC 65nm CMOS; 27.4× & 2.65× energy savings and 10.7× & 1.50× performance for each decoder & encoder. [P.2]
• XGBoost Decision Tree using Modular Unit tree ASIC Design; Led the algorithm optimization, front-end design and
full physical design flow for this digital chip, fabricated in TSMC 65nm CMOS. Optimizing floorplan, PnR, and design
PLL for a high throughput; 42× higher throughput, 253× higher TOPS/W, 404× higher TOPS/mm2, and 72% area
reduction. [P.1] [P.7]
• Mentored and participated multiple tape-out and architecture design projects.
Undergraduate Research Intern, Korea University Seoul, Korea
- VLSI Signal Processing LAB (Advisor: Prof. Park, Jong-Sun) Sep. 2021 – Dec. 2021
• Enhanced Stability of 8T and 10T SRAM over 6T SRAM with monte carlo simulation.
- Bio-Application System & IC LAB (Advisor: Prof. Lee, Hyung-Min) Jan. 2021 – Jun. 2021
• Design of Low-Dropout (LDO) Linear Regulator ICs With Advanced Transient Response
Undergraduate Research Intern, Nanyang Technological University Nanyang, Singapore
- Nano-scale Integrated Circuits for Excellence LAB (Advisor: Prof. Kim, Tony Tae-Hyoung) Jun. 2021 – Aug. 2021
• Research on Computing-In-Memory: Analyzed Ambit In-Memory Accelerator & Advanced Computer Architecture
INVITED TALK/SEMINAR
“ML Accelerator from Edge to Data Center with Emerging Application and Processing In-Memory”
Invited Seminar; VLSI System Lab, Yonsei University, Seoul, Korea Jun. 2025
“Hybrid SLC-MLC RRAM Mixed-Signal Processing-in-Memory Architecture for Transformer Acceleration via
Gradient Redistribution”
Invited Session in Mondays in Memory (MiM) Webinar Dec. 2025
TEACHING EXPERIENCE
Teaching Assistant for CSE 140, “Components and Design Techniques for Digital Systems”, UCSD Jan. 2025 – Mar. 2025
PATENTS
[2] C. E. Song, “Three-dimensional flash memory with back gate”, US11688462B2, United States, 2023
[1] C. E. Song, “Method and System for Providing Virtual Reality Space”, 10-2368-9530000, Republic of Korea, 2022
SKILLS
Languages: C/C++, Python, Verilog, SystemVerilog, MATLAB, Linux OS, Server Management
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HW Tools: Model Sim, Design Vision, iverilog, Cadence - Virtuoso, Genus, Innovus, Xcelium, simvision, Pspice / Synopsys -
Design Complier, VCS, DVE
HONORS & AWARDS
IEEE Solid-State Circuits Society Student Travel Grant Award (STGA) Dec. 2025
Korean Honor Scholarship, Embassy of the Republic of Korea in the USA (Ministry of Foreign Affairs, Korea) Sep. 2025
Best Doctoral Research Award, Computer Science and Engineering, UCSD Jun. 2025
ISCA Student Travel Grant Award Jun. 2025
Samsung Electronics Global Talent Ph.D, Samsung Electronics Memory Division Solution Oct. 2023
Hackers Family Scholarship, 21st Hackers Bridge Scholarship Jun. 2022
Fund Scholarship, College of Engineering: Apple & San Francisco Alumni Association of Korea University Feb. 2022
Seongnam Scholarships, Seongnam City Scholarship Association Mar. 2021
Dean’s List on 2nd Semester of 2020, Korea University Feb. 2021
Semester High Honors at School of Engineering, Korea University: 2021, 2020, 2017
Top-honor Scholarships at School of Electrical Engineering, Korea University: 2021, 2020, 2017, 2016