my Research

• Efficient Transformer Acceleration via Reconfiguration for Encoder and Decoder Models and Sparsity-Aware Algorithm Mapping

1. This project proposes an innovative solution to efficiently support both encoder and decoder stages, maximizing PE utilization and parallelism

2. Leading front & backend part (RTL design, synthesis & PNR)

3. Accepted by ISLPED 2024

• Hyperdimensional Computing with ReRAM ASIC: A Reconfigurable and Energy-Efficient Approach

(Sponsored by PRISM Center, SRC)

1. Mixed-Signal Chip Fabricated

2.  Front & backend part of analog controller (RTL design, synthesis & PNR, and gds2)

3. Prototype fabricated in a TSMC 40nm CMOS technology

4. To be updated

• HDnn: A Hybrid Hyperdimensional Computing Accelerator for On-Chip Inference and Few-Shot Learning 

(Sponsored by PRISM Center, SRC)

1. Digital Chip Fabricated & Measured

2. Front & backend part (RTL Design, synthesis & PNR, gds2, and measurement)

3. Prototype fabricated in a TSMC 40nm CMOS technology with 11.3mm^2 die area

4. Accepted by ESSERC 2024

• XGBOOST Decision Tree using Modular Unit tree ASIC Design

(Sponsored by KETI, Seongnam-si, Korea)

1. Digital Chip Fabricated & Measured

2. Leading front & backend part (Algorithm Simulation, RTL Design, synthesis & PNR, gds2, and measurement)

3. Prototype fabricated in a TSMC 65nm CMOS technology with 2.8mm^2 die area at the throughput of 1.0 G tree operations/s, 1.16 TOPS, 19 fJ/node, and 52.5 TOPS/W

4. Accepted by CICC 2024